In this paper, we describe an optimization for binary radix-16 (modiï¬ed) Booth recoded multipliers to reduce the maximum height of the partial product columns to [n/4] for n = 64-bit unsigned operands. This is in contrast to the conventional maximum height of [(n + 1)/4].Therefore ,a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of n.
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IJRTI — journal style
"64-Bit Radix_16 Booth Multiplier Using Partial Products", IJRTI - International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.3, Issue 4, page no.29 - 34, April-2018, Available :https://ijrti.org/papers/IJRTI1804006.pdf
APA — 7th edition
Kumar, M. V. A., Kumar, M. B., Chethan, F. A., & Krishna, M. R. (2018). 64-Bit Radix_16 Booth Multiplier Using Partial Products. International Journal for Research Trends and Innovation, 3(4), 29 - 34. https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006
MLA — 9th edition
Kumar, M.V.Akhil, et al. "64-Bit Radix_16 Booth Multiplier Using Partial Products." International Journal for Research Trends and Innovation, vol. 3, no. 4, 2018, pp. 29 - 34, https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006.
Chicago — 17th, bibliography
Kumar, M.V.Akhil, et al. "64-Bit Radix_16 Booth Multiplier Using Partial Products." International Journal for Research Trends and Innovation 3, no. 4 (2018): 29 - 34. https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006.
Harvard — author–date
Kumar, M.V.A. et al. (2018) '64-Bit Radix_16 Booth Multiplier Using Partial Products', International Journal for Research Trends and Innovation, 3(4), pp. 29 - 34. Available at: https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006
IEEE — numbered reference
M. V. A. Kumar, M. B. Kumar, F. A. Chethan and M. R. Krishna, "64-Bit Radix_16 Booth Multiplier Using Partial Products," IJRTI, vol. 3, no. 4, pp. 29 - 34, Apr. 2018.
Vancouver — biomedical
Kumar MVA, Kumar MB, Chethan FA, Krishna MR. 64-Bit Radix_16 Booth Multiplier Using Partial Products. IJRTI. 2018 Apr;3(4):29 - 34.
AMA — 11th edition
Kumar MVA, Kumar MB, Chethan FA, Krishna MR. 64-Bit Radix_16 Booth Multiplier Using Partial Products. IJRTI. 2018;3(4):29 - 34. Accessed at https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006
BibTeX — Zotero, Mendeley, LaTeX
@article{IJRTI1804006,
author = {M.V.Akhil Kumar and M.Bharath Kumar and F.Antony Chethan and M.Rama Krishna},
title = {64-Bit Radix_16 Booth Multiplier Using Partial Products},
journal = {International Journal for Research Trends and Innovation},
volume = {3},
number = {4},
pages = {29 - 34},
year = {2018},
month = {April},
issn = {2456-3315},
url = {https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006}
}
RIS — EndNote, RefWorks
TY - JOUR
AU - Kumar, M.V.Akhil
AU - Kumar, M.Bharath
AU - Chethan, F.Antony
AU - Krishna, M.Rama
TI - 64-Bit Radix_16 Booth Multiplier Using Partial Products
T2 - International Journal for Research Trends and Innovation
JA - IJRTI
VL - 3
IS - 4
PY - 2018
SN - 2456-3315
UR - https://ijrti.org/viewpaperforall.php?paper=IJRTI1804006
SP - 29
EP - 34
ER -
International Journal for Research Trends and InnovationPublished by IJRTI (JW Publication)
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Acknowledgements
The authors would like to thank the reviewers and the editorial board of International Journal for Research Trends and Innovation for their careful reading and constructive comments, and all colleagues who supported the preparation of this manuscript.