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Advanced Encryption Standard (AES) is a Federal Information Processing Standard (FIPS) and ordered as Computer Security Standard. The AES calculation is a square figure that can scramble and unscramble computerized data. The AES calculation is equipped for utilizing cryptographic keys of 128, 192 and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) and it is well suited for hardware. We have worked with the pipelining structure and modifications such as merging of Sub bytes and Shift Rows, and optimization of each clock cycle to incorporate maximum number of operations etc. have been successfully implemented. The encryption and decryption process of Rijndael algorithm was captured in VHDL language and corresponding FPGA implementation resulted in reduced number of slices (6901) and an achieved a data throughput of 38.346 Gbps which is implemented on Xilinx 13.2.
"VLSI Based Implementation of Multi-Round AES Algorithm for Text Security: A Review", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.4, Issue 2, page no.35 - 38, February-2019, Available :http://www.ijrti.org/papers/IJRTI1902007.pdf
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator