Design of DTMF chip using VHDL and, FPGA synthesis
IJRTI1905054
Volume 4, Issue 5
Page 233 - 236
May 2019
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ISSN2456-3315
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Paper Title
Design of DTMF chip using VHDL and, FPGA synthesis
Authors
Himani , Dr. A. K Gautam
Keywords
DTMF Keypad, VHDL Programming, FPGA Synthesis
Abstract
t-The DTMF keypad is widely used input peripheral in many embedded devices and different electronics circuits. The device considers the inputs as the alphabets and numbers and gives to the system for next level of processing. In DTMF dial telephone, a key is presented with a grouping of two sine waves. The dual tones of DTMF are referred as row and column frequencies of keypad. DTMF is the global standard for audible tones that represents the digits on a phone keypad. In the research paper, the DTMF chip is designed and synthesized on SPARTAN-3E FPGA and programmed with the help of VHDL code to display the digits 1, 2, 3, A, 4, 5, 6, B, 7, 8, 9, C, *, 0, #, D. The programming is done in Xilinx ISE 14.2 software and simulated in Modelsim 10.0 software.
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IJRTI — journal style
"Design of DTMF chip using VHDL and, FPGA synthesis", IJRTI - International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.4, Issue 5, page no.233 - 236, May-2019, Available :https://ijrti.org/papers/IJRTI1905054.pdf
APA — 7th edition
Himani, & Gautam, A. K. (2019). Design of DTMF chip using VHDL and, FPGA synthesis. International Journal for Research Trends and Innovation, 4(5), 233 - 236. https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054
MLA — 9th edition
Himani, and A. K Gautam. "Design of DTMF chip using VHDL and, FPGA synthesis." International Journal for Research Trends and Innovation, vol. 4, no. 5, 2019, pp. 233 - 236, https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054.
Chicago — 17th, bibliography
Himani, and A. K Gautam. "Design of DTMF chip using VHDL and, FPGA synthesis." International Journal for Research Trends and Innovation 4, no. 5 (2019): 233 - 236. https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054.
Harvard — author–date
Himani and Gautam, A.K. (2019) 'Design of DTMF chip using VHDL and, FPGA synthesis', International Journal for Research Trends and Innovation, 4(5), pp. 233 - 236. Available at: https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054
IEEE — numbered reference
Himani and A. K. Gautam, "Design of DTMF chip using VHDL and, FPGA synthesis," IJRTI, vol. 4, no. 5, pp. 233 - 236, May. 2019.
Vancouver — biomedical
Himani, Gautam AK. Design of DTMF chip using VHDL and, FPGA synthesis. IJRTI. 2019 May;4(5):233 - 236.
AMA — 11th edition
Himani, Gautam AK. Design of DTMF chip using VHDL and, FPGA synthesis. IJRTI. 2019;4(5):233 - 236. Accessed at https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054
BibTeX — Zotero, Mendeley, LaTeX
@article{IJRTI1905054,
author = {Himani and A. K Gautam},
title = {Design of DTMF chip using VHDL and, FPGA synthesis},
journal = {International Journal for Research Trends and Innovation},
volume = {4},
number = {5},
pages = {233 - 236},
year = {2019},
month = {May},
issn = {2456-3315},
url = {https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054}
}
RIS — EndNote, RefWorks
TY - JOUR
AU - Himani
AU - Gautam, A. K
TI - Design of DTMF chip using VHDL and, FPGA synthesis
T2 - International Journal for Research Trends and Innovation
JA - IJRTI
VL - 4
IS - 5
PY - 2019
SN - 2456-3315
UR - https://ijrti.org/viewpaperforall.php?paper=IJRTI1905054
SP - 233
EP - 236
ER -
International Journal for Research Trends and InnovationPublished by IJRTI (JW Publication)
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Declarations
Funding
No external funding was received for this study.
Conflict of Interest
The authors declare that they have no conflict of interest.
Acknowledgements
The authors would like to thank the reviewers and the editorial board of International Journal for Research Trends and Innovation for their careful reading and constructive comments, and all colleagues who supported the preparation of this manuscript.