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This project presents a design of a one-bit full adder cell supported degenerate pass transistor logic (PTL) using Double Gate MOSFET. The Design cell is degenerate 5-T XOR-XNOR module. This design has been compared with existing one-bit full adder cell supported degenerate pass transistor logic (PTL) designed using Single Gate MOSFET. In this project, the proposed circuit has been analysed for parameters like- power consumption and power delay product. The simulations of the proposed Full Adder performed using DSCH and Micro wind. All the proposed design simulations are administered at 250nm technology for various inputs like supply voltage, temperature and frequency. The decrease of 24% in power consumption has observed in proposed circuit. The results projects a validity of double gate MOSFETs for designing the low power full adder circuit.
Keywords:
Double gate MOSFET,CMOS,Power consumption,low power
Cite Article:
"Design And Analysis Of Double Gate MOSFET Using Full Adder Circuit", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 8, page no.810 - 812, August-2022, Available :http://www.ijrti.org/papers/IJRTI2208140.pdf
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000205198
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator