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Among forward error correcting codes, Turbo codes are the potent error correction method. It performs well because it gets close to the Shannon limit. The Turbo codec, that is discussed in this project, is used to develop the Turbo encoder and decoder. The decoder was created using the Viterbi method, which includes hard-input and hard-output values. In order to estimate error correcting capability, noise is intentionally incorporates into the encoded data. In this situation, the newly created Turbo encoder and decoder are more synchronous to each other by eliminating long strings of zero’s in the encoded data, this will be achieved by scrambling the input data bits by Randomizer. This will decrease the delay of the encoder and decoder and also provide additional unpredictability to the encoded data without changing the encoder's coding rate. The encoder and decoder for the Turbo codec are implemented in Verilog-HDL. Almost in every communication applications, the turbo encoder and decoders are using to encrypt and decrypt the message bits with error correction capability, for example SDR’s (Software Defined Radio’s). To increase the more randomness in the code and also to increase the synchronization at the decoder end, here we proposing the concept called scrambling the bits (also called Randomization).
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Cite Article:
"Design and Analysis of Synchronous Turbo Codec Using Randomizer on FPGA", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 10, page no.48 - 55, October-2022, Available :http://www.ijrti.org/papers/IJRTI2210008.pdf
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator