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Sum of Absolute Difference is a popular technique for video encoding, however it is difficult to compute. The adder compressor is used to combine the fragmentary SAD value that is produced from the absolute difference of two video blocks. The high performance SAD architecture using an Brent Kung Adder is described in this paper. In digital circuits like multipliers, where several multi-bit operands must be added simultaneously, adder compressors have been widely employed. In this paper 8-2 adder compressor is designed and pipeline of eight 8-2 adder compressor is constructed, using Verilog HDL with different mixture for the recombination line. The output obtained from the simulation, schematic and synthesis show that Brent Kung Adder (BKA) is more effective and consumes less power then the other adder used in recombination line. The implementation of the design is done in Xilinx’s Vivado 2018.
Keywords:
Adder compressor, BKA, SAD, Verilog HDL.
Cite Article:
"IMPLEMENTATION OF LOW POWER AND AREA EFFICIENT SUM OF ABSOLUTE DIFFERENCE ARCHITECTURE USING BRENT KUNG ADDER", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 10, page no.697 - 704, October-2022, Available :http://www.ijrti.org/papers/IJRTI2210095.pdf
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ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator