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International Journal for Research Trends and Innovation
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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Volume 11 | Issue 4
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Impact Factor : 8.14
Issue per Year : 12
Volume Published : 11
Issue Published : 119
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| Paper Title: | Design and Simulation of a 32bit Ultra Low Power SAR ADC with Digital calibration Using 180nm CMOS Technology |
| Authors Name: | K.Rushendrababu , T. Naga Malleswari , V. Anookhya , T. Santhosh Kumar , M. Sita Sri |
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IJRTI_210668
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| Published Paper Id: | IJRTI2603109 |
| Published In: | Volume 11 Issue 3, March-2026 |
| DOI: | |
| Abstract: | This work presents the design and simulation of an ultra-high-resolution 32-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) optimized for low-power sensing applications. Unlike previous implementations based on the 250 nm process, this design uses an advanced 180 nm CMOS technology, providing significant benefits such as reduced capacitance, lower dynamic power consumption, and smaller silicon area, thereby accuracy. The enabling better energy efficiency and faster operation without compromising architecture incorporates a segmented capacitive DAC with monotonic switching, a dynamic comparator with offset compensation, bootstrapped sampling switches, and energy-aware SAR logic with clock gating. To maintain accuracy at ultra-high resolution, digital calibration and mismatch error correction techniques are integrated. The entire design flow—schematic, simulation, and layout—is implemented using Tanner EDA tools (S-Edit, T-Spice, L-Edit). Simulation results demonstrate that the proposed 32-bit SAR ADC achieves the target resolution with ultra-low power operation, making it highly suitable for medical instrumentation, IoT sensors, aerospace systems, and precision metrology applications. |
| Keywords: | Analog-to-digital converter (ADC), successive approximation register (SAR), low power, energy efficiency |
| Cite Article: | "Design and Simulation of a 32bit Ultra Low Power SAR ADC with Digital calibration Using 180nm CMOS Technology", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.11, Issue 3, page no.b53-b57, March-2026, Available :http://www.ijrti.org/papers/IJRTI2603109.pdf |
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2603109
Registration ID:210668
Published In: Volume 11 Issue 3, March-2026
DOI (Digital Object Identifier):
Page No: b53-b57 Country: krishna, ANDHRA PRADESH, India Research Area: Electronics & Communication Engg. Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2603109 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2603109 |
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED,
Journal Starting Year (ESTD) : 2016
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