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International Journal for Research Trends and Innovation
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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.14 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI)

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Impact Factor : 8.14

Issue per Year : 12

Volume Published : 8

Issue Published : 85

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Article Published : 4010

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Paper Title: Design for SIMD MAC Unit Using 2-Bit Adders and Multipliers
Authors Name: Sagar D , Dr Kiran V
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IJRTI_184411
Published Paper Id: IJRTI2210098
Published In: Volume 7 Issue 10, October-2022
DOI:
Abstract: The advent of digital circuits made it easy to realize many mathematical operations using the binary Boolean functions. The only problem was that the mathematical operations were able to run at a significantly high speed with great accuracy for unsigned or signed integer numbers. Various architectures were able to accelerate the performance of mathematical operations on integers. But most of the real-world problems required operation with real numbers and hence either fixed point or more importantly floating-point arithmetic was necessary. It is possible to run different algorithms to execute operations on floating point numbers in an architecture designed for integer numbers. But the amount of CPU cycles required increases substantially with the complexity of problems involved, the precision required and accuracy as well. It is possible to develop architectures for fixed-point real numbers. But the reusability of the architecture is quite difficult for higher precision. For high accuracy or precision, the architecture hardware utilization increases exponentially. The conversion of fixed point to floating-point increases hardware as well. Hence, we have the IEEE 754 format for single/double precision floating-point architecture. But the amount of power spent, and the hardware requirement is equally high. The time required to produce a stable output is quite high and the floating-point computation is the basic requirement in the overall algorithm of neural networks.
Keywords: Mathematical operations, ALU, CPU, Vedic algorithm, Adders, Multipliers
Cite Article: "Design for SIMD MAC Unit Using 2-Bit Adders and Multipliers", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 10, page no.723 - 730, October-2022, Available :http://www.ijrti.org/papers/IJRTI2210098.pdf
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ISSN: 2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID: IJRTI2210098
Registration ID:184411
Published In: Volume 7 Issue 10, October-2022
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Page No: 723 - 730
Country: Ramanagara, Karnataka, India
Research Area: Electronics & Communication Engg. 
Publisher : IJ Publication
Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2210098
Published Paper PDF: https://www.ijrti.org/papers/IJRTI2210098
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED
Journal Starting Year (ESTD) : 2016

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