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Technology and speed have always progressed hand in hand, from low scale integration to large and very large scale integration and from megahertz (MHz) to gigahertz (GHz). Similarly the system requirements are also rising up with this continuous advancement in process of technology and speed of operation. It is known that low power flipflops are crucial for the design of low-power digital systems. In this paper we analyse the details of various flip-flop design and optimization of various parameters. We have reviewed and studied lowest power flip-flops and compared their performances in the areas of Cost, Power consumption, Delay etc.
Keywords:
Low Power Flip-Flop, Power Consumption, Area, Cost
Cite Article:
"Design and analysis of flip flop for low power VLSI applications - A Review", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.2, Issue 2, page no.9 - 18, February-2017, Available :http://www.ijrti.org/papers/IJRTI1702003.pdf
Downloads:
000204860
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator