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To evaluate the NAND flash memory model I proposed the switching-voltage detector circuit and compensation circuits for low-voltage CMOS inverter. The switching voltage of inverter is an vital parameters in a digital circuit, and it is decided by way of the threshold voltages distinction between MOSFETs.The switching voltage is varying in a fabrication manner . To discover this problem, I developed a threshold voltage detector circuit. Here I additionally carried out the adiabatic logic circuits for decreasing energy dissipation in NAND flash memory .The adiabatic method reduces the energy dissipation during CMOS transistor switching events.I generally targeted to decrease the whole power consumption in NAND flash memory model.
Keywords:
NAND Flash,Adiabatic,CMOS,power dissipation,low power
Cite Article:
"Implementation of NAND flash memory using adiabatic logic circuits", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 8, page no.578 - 580, August-2022, Available :http://www.ijrti.org/papers/IJRTI2208098.pdf
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ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator