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International Journal for Research Trends and Innovation
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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Issue: March 2026
Volume 11 | Issue 3
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Impact Factor : 8.14
Issue per Year : 12
Volume Published : 11
Issue Published : 118
Article Submitted : 21574
Article Published : 8528
Total Authors : 22430
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| Paper Title: | Design and Analysis of a Low-Voltage, Low-Power Double-Tail Dynamic Comparator for Advanced CMOS Technologies |
| Authors Name: | Seva Lalitha , C R K Gayatri |
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IJRTI_207941
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| Published Paper Id: | IJRTI2511151 |
| Published In: | Volume 10 Issue 11, November-2025 |
| DOI: | |
| Abstract: | The increasing shift toward portable, battery-operated intelligent electronic systems demands analog building blocks capable of operating at low voltages while maintaining high-speed and low-power characteristics. Comparators, serving as the fundamental element of analog-to-digital converters (ADCs), significantly influence the overall resolution, speed, and energy efficiency of the conversion process. Traditional topologies, while offering sufficient performance at moderate voltages, experience severe degradation as supply levels scale down in deep submicron technologies. This paper presents a detailed analysis and complete architectural redesign of a low-voltage, low-power double-tail dynamic comparator tailored for advanced CMOS nodes. A modified structure incorporating a shared-charge reset mechanism and adaptive power control is proposed to enhance regeneration speed and reduce unnecessary energy expenditure. Pre-layout and post-layout simulations validate the performance enhancements, demonstrating improved delay, significantly reduced power, and favourable power-delay product (PDP) compared with conventional dynamic and double-tail comparators. The proposed approach is highly suitable for high-speed, energy-constrained ADC architectures in IoT, biomedical, and wireless sensing applications. |
| Keywords: | Dynamic Comparator, Double-Tail Comparator, Low-Power Analog Design, High-Speed ADC, CMOS, Regenerative Latch. |
| Cite Article: | "Design and Analysis of a Low-Voltage, Low-Power Double-Tail Dynamic Comparator for Advanced CMOS Technologies", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.10, Issue 11, page no.b461-b465, November-2025, Available :http://www.ijrti.org/papers/IJRTI2511151.pdf |
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2511151
Registration ID:207941
Published In: Volume 10 Issue 11, November-2025
DOI (Digital Object Identifier):
Page No: b461-b465 Country: -, -, India Research Area: Engineering Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2511151 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2511151 |
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED,
Journal Starting Year (ESTD) : 2016
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