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This paper evaluates the solutions to the problems that occur in processors when handling Interrupts. When processor enters into interrupt handling mode the Instructions which are present in the various stages of the pipeline must be flushed out and the address of the handler is loaded into PC (program counter). This flushing of the pipeline causes loss of many clock cycles which affects efficiency. This paper tackles this problem and improve the overall performance of the processor. The technique discussed in this paper can also be extended to Branches with return values in conjunction with branch predictors.
Keywords:
Pipelined processors, Clock Cycles, Precise Interrupts, Stack Space
Cite Article:
"Efficiently Handling of Content in Pipeline Stages on Interrupts in Processors", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.1, Issue 3, page no.79 - 82, December-2016, Available :http://www.ijrti.org/papers/IJRTI1612013.pdf
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000205113
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator