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High speed finite impulse response (FIR) filter designs are accomplished using the conviction of rounded truncated multipliers. We consider both the optimization of bit width and hardware resources without immolating the frequency response and output signal precision. Total area cost is reduced by using a non uniform coefficient quantization with proper filter order. Multiple constant multiplication/accumulation in a direct FIR structure is designed using an improved version of truncated multipliers. Instead of normal multiplier we are using booth multipliers to reduce the partial products and carry select adder to reduce the delay. Comparisons with previous FIR design approaches show that the proposed designs attain the best area and power results.
Keywords:
Finite impulse response, Multipliers, Bit width, Adders,Radix-4,accumulation, optimization, BEC
Cite Article:
"HIGH SPEED FIR FILTER USING CSLA AND BOOTH MULTIPLIER", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.2, Issue 4, page no.247 - 253, April-2017, Available :http://www.ijrti.org/papers/IJRTI1704057.pdf
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000205135
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator