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International Journal for Research Trends and Innovation
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
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Impact Factor : 8.14
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| Paper Title: | Field Programmable Gate Array with Virtualization and Dynamic Channel Allocation: An Efficient Solution for Deep Learning Algorithms |
| Authors Name: | Shivaprasad Rai B , Dr. Chethana R Murthy |
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| Author Reg. ID: |
IJRTI_183099
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| Published Paper Id: | IJRTI2207142 |
| Published In: | Volume 7 Issue 7, July-2022 |
| DOI: | |
| Abstract: | Field Programmable Gate Array (FPGA) is a computational unit that is used for custom logic implementation. These devices are special due to their flexibility in use. FPGA can be configured and reconfigured when there is a need for a change in the functionality of a connected device. To do any reconfiguration do not need to physically remove the connected FPGA hardware. FPGAs are also a better solution if looking for enhancing the existing hardware infrastructure for advanced usage. Increased execution lifetime is also an added advantage when we consider FPGAs for our implementation. Fetching data for computation is a very critical process when we execute any application on either our Personal Computer or in datacenter servers. If the CPU is involved in every data read/write operation then it becomes overhead for the processor because of this the total performance of the system will degrade. The direct Memory Access controller is an external device that takes care of data transfer in both CPU registers to memory and memory to memory. The MCDMA IP for PCI Express enables the efficient transfer of data using multiple DMA channels between the host and device. The flexible nature of an FPGA arises with the considerable overhead in size, time, and energy usage: an FPGA requires approximately much more area when compared with a normal Application Precise IC component, and also gives slower performance when considering the speed of computation with Application Specific IC and needs much more dynamic power. This drawback is due to FPGA’s programmable routing fabric which needs more space, computation time, and energy to implement “immediate” fabrication. Reprogrammable hardware devices used for performance enhancement have the drawbacks that the connecting functionality provided by hardwired IP blocks covers only the lower protocol layers, and a huge effort is required to achieve high-throughput data transmission between host and accelerator devices. MCDMA for PCI Express operates using a FIFO data structure that stores descriptors, the descriptor queue is set up by the driver program to move data between FPGA and host. Its program fetches descriptors and processes them to get transmission data. To improve the performance, different descriptor queue structures can be used for host-to-device and device-to-host operations for each channel. On the user logic side, we can use memory-mapped and streaming interfaces which will allow for easy integration of the Multi-Channel Direct Memory Access Intellectual Property with other Platform Designer components. In summary, introducing Single Root IO Virtualization on the physical function which supports the creation of virtual functions, and using dynamic channel allocation, can achieve enhanced speed and performance efficiency. With this experiment, we got an 8.49% performance enhancement in terms of bandwidth, when SRIOV and DCA are enabled. |
| Keywords: | Field Programmable Gate Array, Deep Learning, Performance enhancement, Single Root IO Virtualization, Dynamic Channel Allocation |
| Cite Article: | "Field Programmable Gate Array with Virtualization and Dynamic Channel Allocation: An Efficient Solution for Deep Learning Algorithms", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 7, page no.930 - 936, July-2022, Available :http://www.ijrti.org/papers/IJRTI2207142.pdf |
| Downloads: | 000204894 |
| ISSN: |
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016 An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator |
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Published Paper ID: IJRTI2207142
Registration ID:183099
Published In: Volume 7 Issue 7, July-2022
DOI (Digital Object Identifier):
Page No: 930 - 936 Country: Bangalore, Karnataka, India Research Area: Computer Science & Technology Publisher : IJ Publication Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2207142 Published Paper PDF: https://www.ijrti.org/papers/IJRTI2207142 |
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED,
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