CSA carry save adder ALU arithmetic and logical unit, MAC multiply and accumulate unit, RTL register transfer level, UCF user constrain file
Abstract
Multiplication has some limits and to overcome these limitations a new approach has been describe and designed a vedic multiplier with proposed unique addition structure, which is used to perform addition of partially generated products. To meet main concern ‘Speed’ and ‘area’ we have came up with a need particular high speed ALU, the speed of ALU greatly depends upon the speed of multiplication unit used in it. There are so many multiplication techniques exist now a days at algorithmic and structural level. It is been proved that vedic multiplicationis the fastest multiplication approach but there are some other multiplication techniques which are batter then vedic multiplication in terms of chip area. Proposed work is a new architecture of 16 bit vedic with combination of 4 bit vedic multiplications and that 4 bit multiplication is been have developed with a unique addition structure. The observed results are been very good and optimised. Later on ALU module is been developed. the tool used for the designing is Xilinx XST and the target platform for validation is Vertex family vertex-4 FPGA, the preferred language is VHDL
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IJRTI — journal style
"VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER", IJRTI - International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2456-3315, Vol.4, Issue 3, page no.119 - 122, March-2019, Available :https://ijrti.org/papers/IJRTI1903026.pdf
APA — 7th edition
Malviya, U. K., Kumar, G., & Rathore, V. S. (2019). VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER. International Journal for Research Trends and Innovation, 4(3), 119 - 122. https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026
MLA — 9th edition
Malviya, Utsav Kumar, et al. "VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER." International Journal for Research Trends and Innovation, vol. 4, no. 3, 2019, pp. 119 - 122, https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026.
Chicago — 17th, bibliography
Malviya, Utsav Kumar, Gopal Kumar, and Vivek Singh Rathore. "VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER." International Journal for Research Trends and Innovation 4, no. 3 (2019): 119 - 122. https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026.
Harvard — author–date
Malviya, U.K., Kumar, G. and Rathore, V.S. (2019) 'VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER', International Journal for Research Trends and Innovation, 4(3), pp. 119 - 122. Available at: https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026
IEEE — numbered reference
U. K. Malviya, G. Kumar and V. S. Rathore, "VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER," IJRTI, vol. 4, no. 3, pp. 119 - 122, Mar. 2019.
Vancouver — biomedical
Malviya UK, Kumar G, Rathore VS. VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER. IJRTI. 2019 Mar;4(3):119 - 122.
AMA — 11th edition
Malviya UK, Kumar G, Rathore VS. VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER. IJRTI. 2019;4(3):119 - 122. Accessed at https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026
BibTeX — Zotero, Mendeley, LaTeX
@article{IJRTI1903026,
author = {Utsav Kumar Malviya and Gopal Kumar and Vivek Singh Rathore},
title = {VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER},
journal = {International Journal for Research Trends and Innovation},
volume = {4},
number = {3},
pages = {119 - 122},
year = {2019},
month = {March},
issn = {2456-3315},
url = {https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026}
}
RIS — EndNote, RefWorks
TY - JOUR
AU - Malviya, Utsav Kumar
AU - Kumar, Gopal
AU - Rathore, Vivek Singh
TI - VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER
T2 - International Journal for Research Trends and Innovation
JA - IJRTI
VL - 4
IS - 3
PY - 2019
SN - 2456-3315
UR - https://ijrti.org/viewpaperforall.php?paper=IJRTI1903026
SP - 119
EP - 122
ER -
International Journal for Research Trends and InnovationPublished by IJRTI (JW Publication)
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Declarations
Funding
No external funding was received for this study.
Conflict of Interest
The authors declare that they have no conflict of interest.
Acknowledgements
The authors would like to thank the reviewers and the editorial board of International Journal for Research Trends and Innovation for their careful reading and constructive comments, and all colleagues who supported the preparation of this manuscript.