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Multiplication has some limits and to overcome these limitations a new approach has been describe and designed a vedic multiplier with proposed unique addition structure, which is used to perform addition of partially generated products. To meet main concern ‘Speed’ and ‘area’ we have came up with a need particular high speed ALU, the speed of ALU greatly depends upon the speed of multiplication unit used in it. There are so many multiplication techniques exist now a days at algorithmic and structural level. It is been proved that vedic multiplicationis the fastest multiplication approach but there are some other multiplication techniques which are batter then vedic multiplication in terms of chip area. Proposed work is a new architecture of 16 bit vedic with combination of 4 bit vedic multiplications and that 4 bit multiplication is been have developed with a unique addition structure. The observed results are been very good and optimised. Later on ALU module is been developed. the tool used for the designing is Xilinx XST and the target platform for validation is Vertex family vertex-4 FPGA, the preferred language is VHDL
Keywords:
CSA carry save adder ALU arithmetic and logical unit, MAC multiply and accumulate unit, RTL register transfer level, UCF user constrain file
Cite Article:
"VEDIC ALU USING AREA OPTIMISED URDHVA TRIYAMBAKAM MULTIPLIER", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.4, Issue 3, page no.119 - 122, March-2019, Available :http://www.ijrti.org/papers/IJRTI1903026.pdf
Downloads:
000204770
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator