Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.14 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI)
In this paper, we have proposed a Hybrid configurable logic block architecture for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Both accounting for complex logic block and routing area while maintaining mapping depth. For fracturable architectures, the proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Keywords:
: FPGA, CLB’s, Look Up Tables, Multiplexers, Fracturable Architectures.
Cite Article:
"HYBRID CONFIGURABLE LOGIC ARCHITECTURE FOR FPGA’S", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.2, Issue 7, page no.75 - 84, July-2017, Available :http://www.ijrti.org/papers/IJRTI1707014.pdf
Downloads:
000205141
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator