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Full adder circuit is one of the most important digital functional blocks used in Arithmetic and Logical Unit. Adders are the core element of arithmetic operations like addition, multiplication, division, exponentiation etc. In most of the systems adder lies in the critical path that affects the overall speed of the system. This paper presents a novel design of 8T full adder, which is designed on the logic of two 3T XOR and one 2T MUX, so in total of 8 transistors. Compared to other existing 14T ,10T, 9T Full adders the proposed design has significant improvement in power consumption, delay and power delay product. The proposed 8T full adder is implemented using the 90nm technology library and is simulated & verified using the DSCH simulation tool and 3D layout of 8T full adder is designed using Microwind tool. And it observed from the simulation results that the proposed 8T full adder has better performance than the other existing full adders in terms of power consumption, delay PDP (power delay product) and transistor count.
Keywords:
8T Full Adder, high speed, low power
Cite Article:
"High-Speed And Low Power 8T Full Adder Using 3T Ex-OR And 2T Multiplexer", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 8, page no.807 - 809, August-2022, Available :http://www.ijrti.org/papers/IJRTI2208139.pdf
Downloads:
000205262
ISSN:
2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator