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International Journal for Research Trends and Innovation
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ISSN Approved Journal No: 2456-3315 | Impact factor: 8.14 | ESTD Year: 2016
Scholarly open access journals, Peer-reviewed, and Refereed Journals, Impact factor 8.14 (Calculate by google scholar and Semantic Scholar | AI-Powered Research Tool) , Multidisciplinary, Monthly, Indexing in all major database & Metadata, Citation Generator, Digital Object Identifier(DOI)

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Impact Factor : 8.14

Issue per Year : 12

Volume Published : 8

Issue Published : 85

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Article Published : 4010

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Paper Title: Design and Comparative Analysis of 4-Bit RCA for Low Power Applications
Authors Name: E M SAVI TEJA , Dr. KIRAN V
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IJRTI_184414
Published Paper Id: IJRTI2210097
Published In: Volume 7 Issue 10, October-2022
DOI:
Abstract: The active development in the domain of micro-electronic devices, led the need for the designs with high speed, low power dissipation, lower area and urge for several research intentions. There are several design techniques that are available which can be used for the circuit implementation in VLSI design, but a very few design configurations give the optimality at required satisfactory level. This work is keenly focused on reducing the values of delay, power and improve the stability of a 4bit RCA (Ripple Carry Adder), inducing various full adder design techniques. To increase battery life, data from comparative analyses of power, delay, and stability employing complementary metal oxide semiconductors, static energy recovery full adders, full swing gate diffused input, and different transistor counts are implemented. As an advancement to this work, new GDI design technique is implemented and found to be with respect to power, area and delay values in comparison with existing traditional techniques. The Cadence Virtuoso tool with 45nm CMOS technology is used to simulate Power and delay. The results shown an improved performance for the suggested design at a supply voltage of 1.0V in terms of power and latency. According to simulation results, the proposed design shows the least power consumption and a fewer delay than other full adder circuits already in use. As a result, the PDP is enhanced in comparison to other full adder designs.
Keywords: CMOS, SERF, GDI, FS-GDI, Full Adders, PTL, Short Channel Effects.
Cite Article: "Design and Comparative Analysis of 4-Bit RCA for Low Power Applications", International Journal of Science & Engineering Development Research (www.ijrti.org), ISSN:2455-2631, Vol.7, Issue 10, page no.714 - 722, October-2022, Available :http://www.ijrti.org/papers/IJRTI2210097.pdf
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ISSN: 2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publication Details: Published Paper ID: IJRTI2210097
Registration ID:184414
Published In: Volume 7 Issue 10, October-2022
DOI (Digital Object Identifier):
Page No: 714 - 722
Country: Hindupur, Andhra Pradesh, India
Research Area: Electronics & Communication Engg. 
Publisher : IJ Publication
Published Paper URL : https://www.ijrti.org/viewpaperforall?paper=IJRTI2210097
Published Paper PDF: https://www.ijrti.org/papers/IJRTI2210097
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ISSN: 2456-3315
Impact Factor: 8.14 and ISSN APPROVED
Journal Starting Year (ESTD) : 2016

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