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The design and implementation of GDI NOR logic are examined in this project, along with how it may be fused with a half-adder using PASTA logic and then extended to a full-adder using the GDI approach. With fewer transistors and better performance, GDI (Gate Diffusion Input) provides a power-efficient substitute for traditional CMOS logic. Asynchronous addition is made possible using PASTA (Parallel Self-Timed Adder) logic, which improves speed and power efficiency. Using Cadence software, the research puts these designs into practice while examining important performance indicators including area, power consumption, and delay. The findings show that GDI-based designs perform better than traditional techniques in terms of compactness and energy efficiency. The study lays the groundwork for future investigations into intricate arithmetic circuits utilizing GDI and PASTA approaches while also advancing low-power VLSI design
"GDI NOR Logic and half adder fusion using PASTA logic", International Journal for Research Trends and Innovation (www.ijrti.org), ISSN:2455-2631, Vol.10, Issue 3, page no.c16-c20, March-2025, Available :http://www.ijrti.org/papers/IJRTI2503203.pdf
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2456-3315 | IMPACT FACTOR: 8.14 Calculated By Google Scholar| ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.14 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator